FPGA + Breadboard (Intermediate Level)
Simulate a parking lot car counter using digital circuits on a breadboard and FPGA
Ready-to-teach resources
Laboratory Exercises
19 results
Ready-to-teach resources
Laboratory Exercises
19 results
Category:
Simulation
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FPGA + LED Matrix
Implement Conway's Game of Life on an LED Matrix using FPGA
FPGA + Parking Lot (Intermediate Level)
Develop an intermediate-level parking lot management system using FPGA
STM32 Lab Introduction (Keil Studio)
Introduce the UI of STM32 remote lab and Keil Studio Cloud
STM32 Lab Introduction (Arduino IDE)
Introduce the UI of STM32 remote lab and Arduino IDE
STM32 + LED Matrix (Keil Studio)
Display static patterns and animations on an LED Matrix using STM32 and Keil Studio
STM32 + LED Matrix (Arduino IDE)
Display static patterns and animations on an LED Matrix using STM32 and Arduino IDE
STM32 + Parking Lot (Basic Level, Keil Studio)
Develop a basic-level parking lot management system using STM32 and Keil Studio Cloud
STM32 + Parking Lot (Basic Level, Arduino IDE)
Develop a basic-level parking lot management system using STM32 and Arduino IDE
STM32 + Parking Lot (Intermediate Level, Keil Studio)
Develop an intermediate-level parking lot management system using STM32 and Keil Studio
STM32 + Parking Lot (Intermediate Level, Arduino IDE)
Develop an intermediate-level parking lot management system using STM32 and Arduino IDE
FPGA + Automatic Door (Basic Level)
Design and test a safe VHDL controller for the REDTAIL automatic door on a DE1-SoC.
STM32 + Automatic Door (Basic Level, Mbed OS)
Build and test an endpoint-safe Mbed controller for the REDTAIL automatic door on an STM32 NUCLEO-WB55RG.
FPGA + Wiper (Basic Level, VHDL)
Design and test a rain-responsive VHDL controller for the Deusto Wiper simulation on a DE1-SoC.
FPGA + Wiper (Basic Level, SystemVerilog)
Design and test a rain-responsive SystemVerilog controller for the Deusto Wiper simulation on a DE1-SoC.
STM32 + Wiper (Basic Level, Mbed OS)
Build and test a rain-responsive Mbed OS controller for the Deusto Wiper simulation on an STM32 NUCLEO-WB55RG.
FPGA + Wiper 2-Bit (Intermediate Level, VHDL)
Design and test a stateful directional VHDL controller for the Deusto Wiper 2-Bit simulation on a DE1-SoC.
FPGA + Wiper 2-Bit (Intermediate Level, SystemVerilog)
Design and test a stateful directional SystemVerilog controller for the Deusto Wiper 2-Bit simulation on a DE1-SoC.
STM32 + Wiper 2-Bit (Intermediate Level, Mbed OS)
Build and test a stateful directional Mbed OS controller for the Deusto Wiper 2-Bit simulation on an STM32 NUCLEO-WB55RG.