FPGA + Automatic Door (Basic Level)

Design, implement, and test a safe VHDL controller for the REDTAIL automatic door using the Altera DE1-SoC. The activity covers endpoint interlocks, mutually exclusive actuator commands, reversal when a person is detected, and structured remote-lab testing.

• Student Activity Handout (PDF) — DE1-SoC Automatic Door with VHDL
• Editable Student Activity Handout (DOCX) — DE1-SoC Automatic Door with VHDL
• Instructor Solution (ZIP) — DE1-SoC Automatic Door with VHDL Instructor approval is required. Contact the REDTAIL team about access. Already approved? Log in.