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Laboratory exercise

FPGA + Wiper 2-Bit (Intermediate Level, VHDL)

By: WebLab-Deusto (University of Deusto) , Giovanna Lani (WebLab-Deusto, University of Deusto)

Description

Design, implement, and test a stateful two-bit windshield-wiper controller using VHDL and the Altera DE1-SoC. The activity covers the deployed endpoint-name compatibility contract, four command states, direction retention across dry pauses, immediate endpoint reversal, simultaneous-sensor fault output, and structured remote-lab testing.