FPGA + Automatic Door (Basic Level)
Design and test a safe VHDL controller for the REDTAIL automatic door on a DE1-SoC.
Ready-to-teach resources
Laboratory Exercises
3 results
Ready-to-teach resources
Laboratory Exercises
3 results
FPGA + Wiper (Basic Level, VHDL)
Design and test a rain-responsive VHDL controller for the Deusto Wiper simulation on a DE1-SoC.
FPGA + Wiper 2-Bit (Intermediate Level, VHDL)
Design and test a stateful directional VHDL controller for the Deusto Wiper 2-Bit simulation on a DE1-SoC.