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Categories:
  • Digital Twin
  • Simulation
Supported Devices:
  • Altera DE1-SoC
    • SystemVerilog
Breadboard (Butterfly)

Simulation

Breadboard (Butterfly)

By: RHLab (University of Washington) , Matt Guo (RHLab, University of Washington)

Connect logic gates in a breadboard

Documents
  • Documentation
Laboratory Exercises
Laboratory Exercises Devices Authors
FPGA + Breadboard (Intermediate Level)
  • Altera DE1-SoC / SystemVerilog
 RHLab (University of Washington), Matt Guo (RHLab, University of Washington)
REDTAIL

Real hardware access for better remote laboratory learning.

Developed by RHLab at the University of Washington with LabsLand.

Exercises Simulations Devices Contact GitHub

This website was supported by the National Science Foundation's Division of Undergraduate Education under Grant #2336745. Source code is available on GitHub. Some content may be provided by third parties or developed outside the REDTAIL project and grant.