Categories:
Supported Devices:
-
Altera DE1-SoC
- VHDL
- Verilog
- SystemVerilog
Simulation: Breadboard (Butterfly)
By: RHLab (University of Washington) , Matt Guo (RHLab, University of Washington)
Description
Connect logic gates in a breadboard
Downloads
- Breadboard (Butterfly) documentation
- Altera DE1-SoC:
Laboratory Exercises
No laboratory exercises available for this simulation.