Categories:
Supported Devices:
-
Altera DE1-SoC
- VHDL
- Verilog
- SystemVerilog
-
STM32 Nucleo WB55RG
- STM32CubeMX
- mbedOS
- Online IDE (STM32CubeMX)
I/O mapping for Altera DE1-SoC
Download Word version Download Markdown versionWatertank DE1-SoC IO mappings
| Signal | Type | GPIO |
|---|---|---|
| Pump 1 bit 0 | FPGA output | GPIO 26 |
| Pump 1 bit 1 | FPGA output | GPIO 27 |
| Pump 2 bit 0 | FPGA output | GPIO 32 |
| Pump 2 bit 1 | FPGA output | GPIO 34 |
| Low sensor | FPGA input | GPIO 28 |
| Mid sensor | FPGA input | GPIO 29 |
| High sensor | FPGA input | GPIO 30 |
| Pump 1 hot sensor | FPGA input | GPIO 23 |
| Pump 1 hot sensor | FPGA input | GPIO 24 |