Categories:
Supported Devices:
-
Altera DE1-SoC
- VHDL
- Verilog
- SystemVerilog
-
STM32 Nucleo WB55RG
- STM32CubeMX
- mbedOS
- Online IDE (STM32CubeMX)
Simulation: Parking Lot
By: RHLab (University of Washington) , LabsLand
I/O mapping for Altera DE1-SoC
Download Word version Download Markdown versionParking Lot DE1-SoC IO mappings
| Signal | Type | GPIO |
|---|---|---|
| Presence Parking Spot 1 | FPGA input | GPIO 28 |
| Presence Parking Spot 2 | FPGA input | GPIO 29 |
| Presence Parking Spot 3 | FPGA input | GPIO 30 |
| Presence Entrance Gate | FPGA input | GPIO 23 |
| Presence Exit Gate | FPGA input | GPIO 24 |
| LED Parking Spot 1 | FPGA output | GPIO 26 |
| LED Parking Spot 2 | FPGA output | GPIO 27 |
| LED Parking Spot 3 | FPGA output | GPIO 32 |
| LED Parking Full | FPGA output | GPIO 34 |
| Open Entrance Gate | FPGA output | GPIO 31 |
| Open Exit Gate | FPGA output | GPIO 33 |