Categories:

Simulation

Supported Devices:

Altera DE1-SoC
- VHDL
- Verilog
- SystemVerilog
STM32 Nucleo WB55RG
- STM32CubeMX
- mbedOS
- Online IDE (STM32CubeMX)

Morse code

Simulation: Morse code

By: RHLab (University of Washington) , Kevin Kuo (RHLab, University of Washington)

I/O mapping for Altera DE1-SoC

Download Word version Download Markdown version

Morse DE1-SoC IO mappings

Signal	Type	GPIO
Morse	FPGA output	GPIO 26